1. Field of the Invention
The present invention relates to a method of designing a threshold element, and to a threshold element designed using such a method. In particular, the invention is adapted to develop a threshold element based on an output wired CMOS (complementary metal oxide semiconductor) logic.
2. Description of the Prior Art
During the last 40 years, the tides of interest to threshold and majority logics rose and waned periodically. This was caused, on the one hand, by new circuit elements of threshold nature and, on the other hand, by the tasks which used threshold functions to specify functional blocks. There are a lot of such tasks, for example, those of reliability, threshold coding, AD/DA-conversion, filtration, etc. Of special note are neural networks, the behavior of formal neutrons in which is described by threshold functions, starting from the classic work by McCulloch and Pitts.
A threshold function is defined as                     y        =                              Sign            ⁡                          (                                                                    ∑                                          i                      =                      1                                        n                                    ⁢                                                            w                      i                                        ⁢                                          x                      i                                                                      -                T                            )                                =                      {                                                            1                                                                                                                                              if                          ⁢                                                      xe2x80x83                                                    ⁢                                                                                    ∑                                                              i                                =                                1                                                            n                                                        ⁢                                                                                          w                                i                                                            ⁢                                                              x                                i                                                                                                                                    -                        T                                            ≥                      0                                        ⁢                                          xe2x80x83                                                                                                                    0                                                                                                                    if                        ⁢                                                  xe2x80x83                                                ⁢                                                                              ∑                                                          i                              =                              1                                                        n                                                    ⁢                                                                                    w                              i                                                        ⁢                                                          x                              i                                                                                                                          -                      T                                         less than                     0                                                                                                          (        1        )            
where wi is the weight of the i-th input and T is the threshold. Thus, a threshold element should consist of an adder and a threshold comparator.
Recently, new circuits of CMOS threshold elements have been suggested and studied. A xcexdCMOS is based on the CMOS-inverter with floating gate and capacity inputs. Another CMOS is based on output wired CMOS inverters. The latter are the subject of the present specification.
FIG. 1 illustrates the structure of a threshold element consisting of output wired CMOS inverters. The threshold element comprises inverters 1, 2, . . . , n having inputs x1, x2, . . . , xn. Outputs of the inverters 1, 2, . . . , n are wired. The output voltage Vout appears at the wired outputs. A decision inverter 10 converts the output voltage Vout into binary data which is the final result y. The threshold value of the decision inverter 10 is determined in proper manner to truly binary-code the result of the majority. The inverters 1, 2, . . . , n realize an adder, while the decision inverter 10 realizes a comparator, in this circuit. The threshold element allows outputs from the inverters 1, 2, . . . , n to cause the tug of war, in which the final result y becomes xe2x80x9c1xe2x80x9d if more binary code xe2x80x9c1xe2x80x9d is in put and becomes xe2x80x9c0xe2x80x9d if more binary code xe2x80x9c0xe2x80x9d is input. Thus, the inverters as a whole establish a majority circuit.
Since threshold functions are a subset of Boolean functions, any threshold function can naturally be represented by a superposition of operations (circuit elements) of any functionally full basis. The question is whether circuits can be built that would implement threshold functions in a simpler way than the traditional circuits do. If the answer is positive, it would be possible to simplify the implementations of arbitrary logic functions having a bigger number of basic elements. In CMOS-implementation, every character entry corresponds to two (p- and n-) transistors.
It is therefore an object of the present invention to provide a threshold element capable of providing the function blocks with transistors less than two for each of the inputs, and a method of designing the same.
According to the present invention, there is provided a method of designing a threshold element, comprising: converting to the form including a ratio related to p- and n-transistors a threshold function which outputs the result of comparison between a predetermined threshold value and the sum of weighted inputs; and allocating the inputs to the p- and n-transistors in accordance with the ratio, so as to design a threshold element corresponding to the threshold function.
The ratio could be a parameter to determine which of p- and n-transistors more affects on the output when the p- and n-transistors are turned on, since the ratio is related to the p- and n-transistors. In other words, the ratio could be a parameter to determine the condition of the above-mentioned tug of war.
A threshold element of the present invention can be designed using the above-mentioned designing method. When a threshold function is converted to the form including a ratio related to p- and n-transistors, respective inputs are ti allocated to the p- and n-transistors in accordance with the ratio.